| 摘要 |
PURPOSE:To reduce an output capacity, an input capacity, and a feedback capacity, by providing a small impurity concentration by making an N<-> layer an epitaxial layer, and by reducing a channel length by the self-aligning of an offset gate. CONSTITUTION:A P<+>P<->N<-> type three layer Si substrate is prepared. A P type well 10 reaching a P<-> type layer 2 form the surface is formed. An N<+> type diffused layers 4 and 5, which are to become a surce and a drain, are formed at a part of the P type well and a part of an N<-> type layer 9. Thereafter, thin insulating film 6 is formed. Mo is evaporated or sputtered on the entire surface and inpurity doped polycrystal Si is deposited. An Mo gate 7 is made to remain on a part of the P-well layer. With the Mo gate as a mask, an N type impurity ions are implanted, and an N<-> offset gate 8 is formed on the surface of the P well. Thereafter an interlayer insulating film 12 is deposited. After a part of it is removed, Al is evaporated, and source and drain electrodes S and D are obtained by performing patterning and hot etching. |
