| 摘要 |
PURPOSE:To decrease the cycle time, by producing the internal address signal to plural memory blocks which can perform the simultaneous reading/writing independently of the input address information. CONSTITUTION:An internal address generating circuit 7 generates the internal addresses on the basis of the address information fed to an address buffer 2 of a memory device 10 for the memory blocks 4a, 4b, etc. which can read and write at one time and independently of each other. Then the parallel accesses are given to the blocks 4a and 4b via the address decorders 3a and 3b respectively. The data is read and written via a data multiplexer 8, an I/O5, etc. Owing to this parallel process, the cycle time is decreased. |
