| 摘要 |
PURPOSE:To prevent the mistake in synthesizing odd and even signals, by supplying two systems of signals respectively to a signal processing circuit consisting of a sample-hold circuit and an A/D conversion circuit, synthesizing them at a data selector circuit, and passing through the result to a latch circuit and a D/A converter. CONSTITUTION:An odd number picture element signal VOO and an even number picture element signal VEO respectively amplified with amplifiers 15a, 15b are inputted to sample-hold circuits 16a, 16b respectively, and sample-held in clock pulses SHCK1 and SHCK2. The signals are inputted to A/D converters 17a, 17b, and A/D-converted with clock pulses ADCK1, ADCK2. They are alternately selected at a data selector 18 with a selection signal SEL, and tentatively stored with a latch control signal LAT at a latch circuit 19, and outputted as a digital coupling signal DCO. They pass through a D/A-converter 20 to obtain signals arranged with correct odd and even numbers. |
