| 摘要 |
A circuit consisting of five cascaded binary coded decimal, UP-DOWN circuits with associated gates, a first input causes the counters to count up, at a 10 Mhz rate until any second input, which latches into memory the accumulated time in the counters, and causes the counters to count down at 5 Mhz rate, when the counters reach zero an output pulse, suitable for triggering photo flash strobes is generated.
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