| 摘要 |
PURPOSE:To speed up an instruction fetch, and to limit the operation of an instruction buffer memory, by providing an instruction buffer memory coupled directly with a main storage device at the inside of an instruction unit, and supplying its contents to the instruction buffer. CONSTITUTION:An instruction buffer memory IBS is provided between a conventional buffer IBF and a main storage device MM, and usually has enough capacity for a single fetch from the main storage device by the buffer memory BS, e.g. 32 bytes. In the figure, a TML is a transmission line. An instruction unit ISU fetches and stores a specific amount of instructions from the main storage device MM without the intervention of the buffer memory BS, and executes them successively. The buffer memory BS only deals with channel processing, etc., through a channel interface CIF. |
