| 摘要 |
PURPOSE:To perform data transfer in high speed, without interrupting the normal processing of a control processor, by directly accessing an RAM serving also as a buffer memory in an instruction fetching cycle. CONSTITUTION:Picture information of an original read by a scanner 1 is stored in an RAM2 (serving also as a buffer memory and an RAM of a control processor CPU3), the data is encoded at a sequential compressor 4, after the encoded data is tentatively stored in the RAM2 and given to an MODEM6 via an interface 5 for data transmission. When the CPU3 accesses the RAM2, a multiplexer 10 selects an address bus AB of the CPU3 and a tri-state buffer 11 connects a data bus DB and the RAM2. During the instruction fetching cycle of the CPU3, the data bus DB and the RAM2 are disconnected, the RAM2 and the scanner 1 or the compressor 4 are connected and picture information is written or read out with DMA transfer. |
