| 摘要 |
A latchable bit switch for use in a digital-to-analog converter comprising four differential pairs of transistors and a capacitor. The first pair are responsive to a digital input signal and an inverse digital input signal while the second pair are cross coupled and are responsive to the output of the first pair. The third pair are responsive to a toggle signal and a latch signal and enable either the first or second pair. The fourth pair are responsive to the output of the first and second pair and enable a bit current to a summing bus. The capacitor is coupled across the output of the first and second pair thereby reducing glitches in the bit current caused by the charging of junction capacitances by the fast transitions of the digital input, toggle, and latch signals.
|
