发明名称 MASTER SLICE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To raise a degree of freedom of wiring and simplify layout of circuit device by extending a pair of wirings in parallel and in the opposite direction and by arranging connecting portions on a line at a right angle to wirings. CONSTITUTION:The poly-Si layers 7c, 7d, 7u are formed on the basic cell 17, contact holes of layers 7c, 7u on the y lattice 8', contact holes of layers 7c, 7d on the y lattice 8<2>, contact hole of layer 7c on the x lattice 9', and contact holes of layers 7u, 7d on the x lattice 9<2>. The layer 7c becomes the poly-Si layer 7alpha, and the layers 7u, 7d are combined and becomes the poly-Si layer 7beta. At the peripheral wiring portion 12, the layers 7u, 7d are combined with other poly-Si layer and become the poly-Si layer 7gamma. The layers 7alpha-7gamma are terminated by a pair of contact holes 10. The contact hole of layer 7alpha is located on the lattice 9', the contact hole of layers 7beta, 7gamma are located on the lattice 9<2> and these layers are alternately arranged like layers 7gamma, 7alpha, 7beta, 7alpha,... A pair of layers 7alpha-7gamma alternately arranged provide the common y lattice 8<11>, 8<12>, 8<21>,...
申请公布号 JPS5874052(A) 申请公布日期 1983.05.04
申请号 JP19810174301 申请日期 1981.10.29
申请人 NIPPON DENKI KK 发明人 FUJIKI KUNIMITSU;ISHIZAKI YASUTOSHI
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
代理机构 代理人
主权项
地址