Circuit arrangement for transmitting digital signals in a telecommunications device, in particular a PCM PABX telephone system

摘要

In a telecommunications device of this type, e.g. in a PCM PABX system, when signal bits are exchanged between two functional units, delays may occur on the transmission lines (ÜL) and in the gates (LE1) which result in switching errors. In order to avoid a compensation to be performed in individual cases by means of special delay components, a compensating circuit (AGL) is provided at the receiving end which contains a plurality of multiple D-flip-flops (FF1, ..., FF4) serving as buffer memories. The reading of the signal bits into and out of the flip-flops is controlled by two shift registers (SR1, SR2) which are timed by the transmission clock or reception clock and are brought to a defined output condition by the respective frame synchronisation pulses. The delay compensation is thereby performed automatically. <IMAGE>