| 摘要 |
A successive-approximation charge-redistribution analog-to-digital converter includes a binary weighted capacitive ladder for converting the least significant bits of the binary output representation and a resistive ladder for converting the higher order bits of the output representation. To achieve a half least significant bit shift, the capacitor of lowest capacitance in the ladder having a capacitance C is replaced by first and second capacitors each having a capacitance C/2. Each of these capacitors has a first terminal connected to the input of a comparator. Another input of the first capacitor is coupled to the low reference voltage. The second input of the second capacitor is coupled to one-eighth the high reference voltage during the sample phase and to the low reference voltage when the sample phase is completed. The resulting redistribution of charge which occurs at the input to the comparator is equivalent to minus one-half times the charge corresponding to one least significant bit. Thus, the stored sample to be converted is reduced in voltage by one-half least significant bit.
|
