DATA TRANSMISSION CIRCUIT

摘要

A data transmission circuit for CMOS dynamic random access memory devices having a data input buffer for converting TTL input data signals to CMOS logic level data signals and providing true and complement data signals on a pair of data bus lines, a pair of transmission gates for transmitting the true and complement data signals to a pair of true and complement I/O bus lines comprising a pair of similar constitutional I/O bus line pull-up or pull-down circuits between the output lines of the transmission gates and the I/O bus lines for making logic operations on the data bus lines. The I/O bus lines alternate at the time of a writing operation and a I/O bus line equalizing circuit is connected between the true and complement I/O bus lines for equalizing the pair of the I/O bus lines at a high speed, before or after a writing cycle.