发明名称 GENERATING CIRCUIT OF DIVISION PULSE
摘要 PURPOSE:To obtain a division pulse which varies by the levels of two input signals, by making a capacitive connection between the collector of the 1st transistor amplifying circuit and the base of the 2nd transistor amplifying circuit and also a shared connection between the emitters of said amplifying circuits. CONSTITUTION:An inverse amplifying circuit consisting of a transistor TR11 is connected to an inverse amplifying circuit consisting of a TR12 via a capacitor 30. The working power is supplied to terminals 1 and 2, and a terminal 3 is excited by a synchronizing source. The input voltage is applied to terminals 4 and 5, and an output is extracted out of a terminal 6 in the form of a pulse output. When input voltage V1 is low, waveforms (b), (c) and (d) have the operations shown by solid lines (1). While pulse widths T1 and T2 proportional to the voltage V1 are obtained as shown by a 1-dot chain lines (2) when the V1 is high. In case input voltage V2 has a fluctuation, the waveforms become as shown by the chain line (2) and the solid line (1) when the V2 is high and low respectively even if the V1 is constant as shown by a waveform B. Thus the output pulse width is adversely proportional to the V2.
申请公布号 JPS5866414(A) 申请公布日期 1983.04.20
申请号 JP19820098256 申请日期 1982.06.07
申请人 HITACHI SEISAKUSHO KK 发明人 KATOU KAZUO
分类号 H03K5/04;H03K3/353;H03K7/08 主分类号 H03K5/04
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