发明名称 DELAY CIRCUIT
摘要 PURPOSE:To eliminate an effect of a temperature change, by defining the period covering from the breaking time of the output voltage through the time when the linear inclination of the output voltage crosses the reference voltage as a delay time and extracting the output voltge from an output terminal of a capacitor. CONSTITUTION:When input voltage V3 of a low level compared with reference voltage V2 of an input terminal 5 is applied to an input terminal 6, transistors TRQ4 and Q7 are turned off with TRQ5 and Q6 turned on respectively. The currents I1 and I2 of constant current sources 8 and 9 flow to resistances R3 and R4 respectively. The current I3 of a constant current source 10 flows to a resistance R6. The potential at a point (i) drops by a degree equivalent to the voltage drop of the resistance R6, and the potential at a terminal 7 drops by a degree equivalent to the voltage drop between the base and the emitter of a TRQ12. When the voltage V1 of a high level is applied to the terminal 6, the TRQ5 and Q6 are turned off and a capacitor C0 discharges the charged electric charge to flow a current IC. The potential of the point (i) is equal to the power source voltage VCC, and the potential of the terminal 7 drops by a degree equivalent to the voltage drop between the base and the emitter of the TRQ12.
申请公布号 JPS5866415(A) 申请公布日期 1983.04.20
申请号 JP19810165084 申请日期 1981.10.16
申请人 FUJITSU KK 发明人 MATSUMURA TOSHIHIKO
分类号 H03K5/13;(IPC1-7):03K5/13 主分类号 H03K5/13
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