发明名称 INSULATING GATE TYPE FIELD EFFECT TRANSISTOR
摘要 PURPOSE:To suppress a latch-up phenomenon in a parasitic thyristor, by forming a high-impurity concentration semiconductor region, so that a part directly beneath a semiconductor region having the other conductivity type, which is formed through an intermediate semiconductor region having the same conductivity as that of said high-impurity concentration semiconductor region, is thick and a part other than that is thin. CONSTITUTION:An n<+> type region 11, whose specified part on a substrate 1 is made thin, is formed from a thick part. Then, an n<-> drain region 12 is formed so as to bury the region 11. Thereafter, a p-type base region 13 is formed in the region 12. An n<+> type source region 14 is formed in the region 13. Thereafter a poly Si gate electrode 7 is formed on the region 13, which is to become a channel region, through a gate oxide film 6. Since the thick n<+> type drain region 11 having a high impurity concentration is formed directly beneath the region 13, the gain of a parasitic P-N-P Tr can be suppressed to a very low value.
申请公布号 JPS6312174(A) 申请公布日期 1988.01.19
申请号 JP19860156541 申请日期 1986.07.02
申请人 MITSUBISHI ELECTRIC CORP 发明人 MITARAI GORO;SATSUMA KAZUMASA
分类号 H01L29/68;H01L29/739;H01L29/78 主分类号 H01L29/68
代理机构 代理人
主权项
地址
您可能感兴趣的专利