| 摘要 |
PURPOSE:To obtain an access device free of a deadlock by accessing a common bus from a master access device, and inhibiting a deciding circuit from sending a request for use to the common bus for several cycles of the common bus once a response for holding is obtained. CONSTITUTION:When one module connected to a common bus 10 is to access the bus 10, a deciding circuit 1 outputs a request for use to the bus 10 and decides whether the bus is usable or not. When the bus is usable, a master access device 2 accesses the bus 10 repeatedly every time a permission for use is obtained until an acknowledgement or negative acknowledgement response is obtained. When this device 2 receives a holding response, a timer circuit 3 is inhibited from outputting a request for use to the bus 10 for bus cycles in inverse proportion to prescribed priority. Consequently, the bus 10 is not occupied until a response other than the holding response is obtained by a module with higher priority, and even modules with lower priority can use the bus 10. |
