发明名称 DETECTOR FOR ERROR IN CHANNEL COMBINATION
摘要 PURPOSE:To easily current an error in setting by detecting and displaying an erroneous combination of a physical channel to an arrival signal handling device provided in a device, and a logical channel for signal processing in the device. CONSTITUTION:A physical address generated by a channel address generating circuit 101 is supplied to a combination setting circuit 102, an address selecting circuit 105, and a data holding circuit 107. An error detecting circuit 104 compares the signal output of the setting circuit 102 with that of a frame address generating circuit 103 to detect coincidence between the physical and logical addresses of a unit frame, and decides on erroneous setting when there are >=2 pulses, thereby detecting a setting state which corresponds to the physical address. This setting state information is written in a physical address of a storage circuit 106 which is selected by the address setting circuit 105, and then read out of the same physical address to be sent to the data holding circuit 107.
申请公布号 JPS5860846(A) 申请公布日期 1983.04.11
申请号 JP19810159135 申请日期 1981.10.06
申请人 NIPPON DENKI KK 发明人 TAKAYAMA MICHIO
分类号 H04J3/14;H04J3/16 主分类号 H04J3/14
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