发明名称 BALANCED CURRENT MULTIPLIER CIRCUIT FOR A SUBSCRIBER LOOP INTERFACE CIRCUIT
摘要 <p>A balanced multiplier circuit for a subscriber loop interface (SLIC)(100) which provides both loop current to a two-wire bidirectional subscriber loop (12, 14) and suppression of longitudinal signals generated at the two-wire loop input to the SLIC while maintaining the midpoint load voltage at half the available power supply voltage applied to the SLIC.</p>
申请公布号 WO1983001163(A1) 申请公布日期 1983.03.31
申请号 US1982001069 申请日期 1982.08.06
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