| 摘要 |
PURPOSE:To enable to facilitate the addition of wirings in a semiconductor integrated circuit device by forming a conductive layer which extends directly under upper layer wirings forming power source reinforcing lines and using the layer as wirings, thereby increasing the number of wiring channels. CONSTITUTION:A plurality of polysilicon wirings 13, 14 are respectively formed in the same directions (perpendicular to each cell row) directly under power source reinforcing lines 5, 6, and are suitably connected at the prescribed positions to the first layer aluminum wirings 15 of a wiring channel region 4. In this manner, it becomes equivalent to the increase in the number of the second layer aluminum wirings in the amount corresponding to the wirings 13, 14. Accordingly, the number of logic gates can be increased by increasing the number of wirings in the direction perpendicular to the cell row and increasing the number of wirings running in the wiring channel region. |
