发明名称 CHANNEL CONTROLLING SYSTEM
摘要 <p>PURPOSE:To reduce the number of input pins of a channel package or an LSI to the half and share a line test circuit to reduce the gate quantity, by operating OR between two-channel components of input signal lines of an I/O interface and scanning them in time division. CONSTITUTION:Plural channels 103 are connected between a channel controlling part 101 and receivers 220 and 221 which receive I/O interface X and Y signal lines XREQER and YREQER, and their outputs are selected and outputted to drivers 222 and 223. Inputs are scanned in time division and selected by an input register 201 of the channel 103, and the output is held in input registers 202 and 203 of channels X and Y. Outputs of registers 202 and 203 are selected successively in a selecting circuit 204 by the output of a decoder 205 and are applied to an establishing circuit 205. Outputs of registers 202 and 203 are compared with the output of the circuit 204 in the circuit 205; and when a change is detected, the switching of time division is stopped temporarily, and the processing is performed in output registers 207 and 208 of channels X and Y.</p>
申请公布号 JPS5850032(A) 申请公布日期 1983.03.24
申请号 JP19810147466 申请日期 1981.09.18
申请人 HITACHI SEISAKUSHO KK 发明人 SUGIYAMA TAICHI;YADA KIYOSHI
分类号 G06F13/42;G06F1/22 主分类号 G06F13/42
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