| 摘要 |
<p>A phase-locked loop circuit which obtains a signal synchronized in phase with an input signal which includes a synchronizing portion and a data portion includes a voltage controlled oscillator (VCO), frequency/phase comparator (EPC) a phase comparator (PC) and a control mean (8a). The frequency/phase comparator detects both the phase difference and the frequency difference between the input signal and a signal derived from the output of the voltage controlled oscillator, and the phase comparator detects the phase difference between the input signal and a signal derived from the output of the voltage controlled oscillator. The control mean controls the voltage controlled oscillator, during at least some portion of the synchronizing signal portion on the basis of the output of the frequency/phase comparator, and, during the data signal portion, on the basis of the output of the phase comparator.</p> |
