发明名称 SETTING SYSTEM FOR WATCHDOG TIMER
摘要 PURPOSE:To minimize the possibility of a watchdog timer is started during a runaway of a program, by writing data from a processor in the watchdog timer only when a selection signal for selecting the watchdog timer is received. CONSTITUTION:A timer controller 2, when receiving watchdog timer selection data, compares it with set data preset in a comparator 3 and when their coincidence is obtained, a selection signal 8 for selecting a watchdog timer 4 is sent to the timer 4. A processor 1 specifies an address of the timer 4 after that to write data, thereby restarting the timer. In this case, the timer inhibits write data from the processor 1 from being inputted to a counter 6 by the condition of an AND circuit 5 unless the selection signal is supplied from the controller 2, so the timer 4 is never started.
申请公布号 JPS5848156(A) 申请公布日期 1983.03.22
申请号 JP19810147376 申请日期 1981.09.18
申请人 FUJITSU KK 发明人 OONISHI NORIO
分类号 G06F11/30;G06F11/00 主分类号 G06F11/30
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