发明名称 LARGE-SCALE INTEGRATED CIRCUIT WITH REENTRY PIN
摘要 PURPOSE:To generate an input test pattern in a random mode and to test thereby function of an integrated circuit, by preventing the formation of a positive feedback circuit system ranging from an internal circuit to a reentry pin and back to the internal circuit. CONSTITUTION:When the logic function of an integrated circuit is tested, a test pattern generated in a random mode from an input terminal 2 is inputted. When a signal of ''0'' is supplied to an output control pin 9, a signal of ''0'' of ''1'' is given to an input-output switching pin 7, and thereby the output of the first AND gate circuit 11 and that of the second AND gate circuit 12 out of the outputs of an auxiliary gate 6 are made opposite to each other. Therefore, a signal current is checked by a NOR gate 3 and an AND gate 5, even when the test pattern in a random mode which is supplied to an internal circuit 1 is the one forming a positive feedback circuit through the intermediary of a reentry pin.
申请公布号 JPS5844366(A) 申请公布日期 1983.03.15
申请号 JP19810142943 申请日期 1981.09.10
申请人 FUJITSU KK 发明人 SUGIYAMA EIJI
分类号 G01R31/28;G01R31/317;G01R31/3185;H01L21/66;H01L21/822;H01L27/00;H01L27/04 主分类号 G01R31/28
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