| 摘要 |
PURPOSE:To perform a state change detection with high reliability and a simple constitution, by detecting the change of state among the rise, fall and inhibition with each point for the digital input of the process input and output. CONSTITUTION:The input digital signals fed to an input IC from outside are loaded in parallel with prescribed intervals to a shift register SRA with a quartz oscillating circuit OS. The output of the SRA is fed to a shift register SRB of the next stage. The outputs of both registers are detected by a detector XOR. At the same time, the output of the circuit OS is divided by a counter CRT, and the output of this division is fed to the off and on detecting decoders FDC and NDC and then applied to a selector SEL via switches SA and SB. Then an interruption is produced at an interruption producing gate ATNF by an AND of the output SE1 of the selector SEL and the state change detection output DT1. A CPU reads in the state of an input part with a request of the interruption. |
