| 摘要 |
PURPOSE:To obtain a pulse signal exceeding constant width, by controlling a generation timing of an output pulse by the first and second clock pulses whose frequency ratio is 2 to 1. CONSTITUTION:This device is constituted so that when both levels of the first and second clock pulse signals are ''1'', an NAND gate 12 generates an output signal, and when a level of the first clock pulse signal is ''1'' and a level of the second clock pulse signal is ''0'', an NAND gate 13 generates an output signal, therefore, before the NAND gate 13 generates an output signal after the NAND gate 12 has generated an output signal, a time interval of at least a half clock portion of the first clock pulse exists. That is to say, as pulse width of an output signal appearing in a signal output terminal Z, width of only a period being at ''0'' level of a signal applied to the first clock pulse input terminal Y1 is obtained. In this way, an outut signal exceeding constant width is obtained exactly. |
