A MIS transistor circuit including a voltage holding circuit.

摘要

An MIS transistor circuit being capable of being operated alternatively in a reset state or in an active state, includes a voltage holding circuit (7, 70) for hold- lng a power supply voltage (Vcc) applied in each reset state so as to provide a clamped voltage (Vcc*). The clamped voltage (Vcc*) is applied in each active state to desired nodes (N3, N3a) of the MIS transistor circuit as the power supply voltage, so that error operation due to voltage fluctuations in the power supply voltage is prevented. The MIS transistor circuit may be a MIS dynamic memory (Fig 1 and Fig 3) or a clock signal generating circuit (Fig 5).