发明名称 TIME MONITOR SYSTEM
摘要 <p>PURPOSE:To output a subtraction end signal in every priority order relating to types of set data, by adding bits setting the processing priority to the datas written in a memory. CONSTITUTION:First, an external processor sets an address of a memory 3 and a data to a write data set register 1 and write address set register 2 through a data line. In this case, 2-bit D7, D6 are added to the host of initial values D0- D5 as the priority designation bits. Thus, 4 types of the priorities can be designated. The data set in the register 1 is written in the memory 3 through a selector 11. The data are read out from the memory 3 with the address generated at an address counter 4 and set to a subtraction counter 6, allowing to set the priority designation bits to a register 8 at the same time.</p>
申请公布号 JPS5833764(A) 申请公布日期 1983.02.28
申请号 JP19810130561 申请日期 1981.08.20
申请人 NIPPON DENKI KK 发明人 KOYAMA MASAYUKI
分类号 G06F9/48;G06F1/14;G06F11/30;G06F11/34 主分类号 G06F9/48
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