| 摘要 |
PURPOSE:To perform less-distortion digital-to-analog conversion by setting the center of a high-order pulse width signal in the center of one sampling period and the center of a low-order pulse width signal at either end of the high-order pulse width signal. CONSTITUTION:When a latch circuit 3 latches the value N=100 of a high-order bit 8B and a latch circuit 4 latches the value M=100 of a low-order bit 7B, a flip-flop FF5 is set at time 156+64=220, and reset at time 384+164=548 by the 384 time output of a counter 2 through counters N and 64b. An FF6, on the other hand, is set at time 156+14=170 through counters 256-N and 64-M/2, and reset at time 270 through a counter M. Further, it is set again at time 498 through counters 2, N, and 64-M/2 and reset again at time 598 through the counter. |
