| 摘要 |
PURPOSE:To increase values of capacitance read-out without providing additional areas for the read-out region by employment of a silicon substrate with a V-shaped groove on one of the surface and by providing capacitance read-out region in the V-shaped groove. CONSTITUTION:The V-shaped groove 13 is formed by anisotropic etching of an n type epitaxial layer 11 on a P<+> silicon wafer 10. N<+> layers 12 are selectively produced on the n type layer 11 with common electrodes 8 provided and a depletion layer control electrode 6 is provided on the P<+> layer 10. Reverse bias voltage is applied between the electrode 6 and electrodes 8, and as the voltage is increased, the depletion layer 9 is widened so as to come eventually into contact with the surface of the V-groove. In order to use the surfaces of the V-groove as a capacitance read-out region 14, a P<+> layer is produced selectively on the surfaces of the V- groove with an electrode 16 provided, or otherwise an electrode provided through an insulating film or an electrode of Schottky junction structure provided. Variation of capacitance which is read out between the electrodes 16, 18 is such that value of the capacitance is reduced as the reverse bias voltage is increased so that variation of capacitance between the electrodes 16, 18 can be controlled by value of the reverse bias voltage. The V-shaped groove which can provide increased effective surface areas for the capacitance read-out electrode 16 facilitates read-out of wider variation of the capacitance within the small chip area. |
