| 摘要 |
<p>PURPOSE:To attain a phase correction between a received digital signal and a synchronizing clock signal even if he duty ratio of a received digital signal is deteriorated by inhibiting the phase correction of the synchronizing clock signal of a bit synchronizing circuit between a lead and a lag phase. CONSTITUTION:A phase sepervisory circuit 3 receives the output signal CD of a data change point detection circuit 1 and signals (a, b) from a phase control circuit 4 and a reset pulse R1 representing a bit period, discriminates the lead/ lag of the phase of the synchrornizing clock signal with respect to the signal CD from the signals and gives the output of phase signal- (lead) and + (lag) at every bit period. The path between the lead and lag corrections is eliminated by the bit synchronizing circuit and even if the duty ratio of the received digital signal is deteriorated, the phase correction of the recovered clock signal is attained. Since the state transition between the lead and lag phase corrections does not exist, the phase difference is corrected gradually to the synchronizing clock signal CLO with respect to the signal DATA.</p> |
