| 摘要 |
PURPOSE:To quantitatively detect write-state of data through excellent electric data erase, by using a MOS transistor of triplex gate type having an erase gate. CONSTITUTION:A memory cell is constituted with an MOS transistor in which the 2nd conductive layer is in service as a floating gate, the 3rd conductive layers 18A and 18B as control gates, the 1st conductive layer 14 as an erase gate, an N<+> semiconductor layer 19A as a drain and an N<+> semiconductor layer 19C as a source. The control gate is provided on a semiconductor substrate via an insulation film and the floating gate and the erase gate are provided in parallel in the insulation film clipped with the control gate and the substrate. |
