发明名称 MOS DYNAMIC MEMORY
摘要 PURPOSE:To make the operation stable, by providing a circuit means writing a voltage of a power supply voltage or over to a capacitor of memory cell and detecting data with a balanced type sense amplifier without using a dummy cell. CONSTITUTION:A transfer gate transistor TM and an information storage capacitor CM constitute one memory cell 2. Between a preamplifier 3 transmitting and receiving data on a pair of data lines DL, DL through input and output lines I/O, I/O and the data lines DL, DL, transfer gate transistors T9 and T10 the gates of which are connected to a column line CL are connected. A capacitor C1 is connected between the data lines DL and a clock signal line phi3 and a refresh circuit 4 is provided. The data line DL is provided with similar memory cell 2' and refresh circuits 4'.
申请公布号 JPS5823386(A) 申请公布日期 1983.02.12
申请号 JP19810120118 申请日期 1981.07.31
申请人 TOKYO SHIBAURA DENKI KK 发明人 ASANO MASAMICHI;IWAHASHI HIROSHI
分类号 G11C11/407;G11C11/4099;H01L21/8242;H01L27/10;H01L27/108 主分类号 G11C11/407
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