发明名称 MOS STATIC TYPE RAM
摘要 PURPOSE:To improve the circuit integration with simple circuit and stable operation, by providing an NOR gate for an input side of a write circuit and performing write recovery operation. CONSTITUTION:When a write control signal externally changes to an L level, a write control signal WE' formed with a control circuit 7 goes to H level to turn on MOSFETs Q18 and Q19 and to connect the output terminal of a circuit 6 and a common data line CD. When the control signal formed at a circuit 7 is changed to L level, NOR gates G1 and G2 are opened and write is made to one memory cell selected. At the end, the circuit 7 is formed so that the leading of a signal is made faster by a time td than the signal WE'. Thus, through the turning on of Q15 and Q16, since the signal changes to H level while the line CD is kept coupled to the output terminal of the circuit 6, the circuits G1 and G2 are closed and the both outputs attain L level. Thus, the level of the line CD quickly changes to H level for the recovery operation.
申请公布号 JPS5814396(A) 申请公布日期 1983.01.27
申请号 JP19810112146 申请日期 1981.07.20
申请人 HITACHI SEISAKUSHO KK 发明人 TANIMURA NOBUROU
分类号 G11C11/417;G11C11/4096;G11C11/413 主分类号 G11C11/417
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