| 摘要 |
A large scale integrated circuit (LSI) wafer and a method relates to testing same which allows LSI logic chips to be tested on wafer without necessitating equipment involving high-precision step-and-repeat mechanisms, and which further allows chips to be tested individually in the connected-on-module environment. The circuit configuration comprises various circuit structures including latches and combinatorial networks.
<??>The chips and wafers are configured that the LSSD provision already incorporated in the chips can be utilized also for the on-wafer and on-module testing. The arrangements, which can be made with a "cut-away" or "deactivate" or an "extend-usage" approach, include five major extensions in the chip-image design. These are: the incorporation of gating of serial test-data output from the chips, the provision if necessary of supplementary latches on chips, the incorporation of gating of parallel inputs to the chip core, the incorporation of in-chip and/or interchip connections, which can be done in a "self-sufficient" or a "neighbour-assisted" arrangement, and the utilization of chip-layout design for step-and-repeat juxtaposition. In addition to these in-chip extensions, the method requires proper wafer organization and an arrangement of connecting the chip-image array to probe-contact pads on the wafer. |
