发明名称 PHASE LOCKING OSCILLATOR
摘要 PURPOSE:To minimize the amplitude of undesired phase fluctuation, by performing division through a frequency divider down to the greatest common measure of a reference input signal and an output signal of a voltage controlling oscillator and then selecting only an optional pulse among the divided pulses to control the voltage controlling oscillator. CONSTITUTION:The difference of phase between a reference input signal and an output signal of a voltage controlling oscillator has a cycle equal to the reciprocal number of the greatest common measure of the frequencies of these two signals. As a result, the difference of phase between optional pulses of both signals is decided well-definedly. A frequency divider 400 is driven by the output of a voltage controlling oscillator 3 and performs the division down to the greatest common measure. Thus the output of the oscillator 3 is applied to the address of a fixed storage circuit 500 to obtain the output of the circuit 500 corresponding to each output pulse of the oscillator 3. Accordingly, only an optional pulse can be selected among the output pulses of the oscillator 3 by deciding properly the contents to be stored in the circuit 500 and then controlling a gate circuit 600 with the output of the circuit 500.
申请公布号 JPS589436(A) 申请公布日期 1983.01.19
申请号 JP19810091820 申请日期 1981.06.15
申请人 NIPPON DENKI KK 发明人 MUTOU HIROSHI
分类号 H03L7/08;H03L7/197 主分类号 H03L7/08
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