发明名称 CONTROLLER OF DIGITAL KEY SIGNAL
摘要 PURPOSE:To compress or enlarge an edge by a prescribed synchronizing period, by selecting either one of a digital key signal and the signal obtained by giving an integer-fold delay of the sampling period to the digital key signal based on the output of detection of the front and rear edges of the selected signal and an indication. CONSTITUTION:A digital key signal KEY which is produced so as to correspond to a partial region of a digital video signal is supplied to a rough control circuit 38. The circuit 38 is controlled by a control logical circuit 40 to which the data and the control signal are supplied from a microprocessor. An RAM42 within the circuit 38 gives a shift to the signal KEY by a prescribed clock synchronize period. The RAM43 and 44 prescribe the degree of the enlargement and compression by setting the degree of delay at a prescribed level. At the same time, a level comparator 54 detects the front and rear edges. Then the outputs of the RAM43 and 44 are selected based on the output of the above-mentioned detection and an indication given from the circuit 40. As a result, both edges are compressed and enlarged by an integer-fold value of the sampling period.
申请公布号 JPS589475(A) 申请公布日期 1983.01.19
申请号 JP19810107420 申请日期 1981.07.09
申请人 SONY KK 发明人 YAMAMOTO YOSHIKAZU
分类号 H04N5/272;H04N9/74;H04N9/75 主分类号 H04N5/272
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