发明名称 SCHEDULE CONTROLLER
摘要 PURPOSE:To decrease the setting time of a schedule and to prevent missetting, by selecting the contents of a plurality of storage elements arranged corresponding to a control time interval of the schedule at each control time interval. CONSTITUTION:When a mode set switch 16 is connected to a terminal 16a, a weekday set with a weekday setter 5, a name of circuit set with a circuit name setter 6, and an operation pattern set with a storage circuit 14 are stored in a storage section 151 of a central operation processor 15. The circuit 14 is provided with FF circuits arranged corresponding to each control time interval of the operation pattern. The operation pattern stored in the storage section 151 is displayed on a display device 18 by connecting a switch 16 to a terminal 16b. When a display set button switch 17 is closed with the switch 16 connected to the terminal 16a, the operation pattern set at the circuit 14 can be displayed on the device sequentially.
申请公布号 JPS588308(A) 申请公布日期 1983.01.18
申请号 JP19810106018 申请日期 1981.07.06
申请人 MITSUBISHI DENKI KK 发明人 MIZUHARA HIROHISA
分类号 G05B19/02;G05B19/05;G05B19/10 主分类号 G05B19/02
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