| 摘要 |
PURPOSE:To store data of a desired word, by performing a word parallel bit serial operation only for a data of a designated word or only for data other than the designated word. CONSTITUTION:A word selected with a retrieved data, i.e., a word with a register 7 set to ''1'', becomes the objective of a word parallel bit operation. The selector 6 is retrieved and switched to a register 3, a control signal is applied to the retrieved data line of an associative memory cell array in place of the retrieved data, the combination of ''0'' and ''1'' is changed, the OR between the result of retrievel on a signal line 0 and the output of the register 3 is taken at an OR gate 1, the storage of the sum to the register 3 again is repeated to execute the word parallel bit serial operation. As a result, a word line driving circuit 5 is driven, and the output of the circuit 5 is transmitted to a word line W via an AND circuit 8 in the word where the output of the register 7 is at ''1'', and the data is stored without being changed by the word of ''0''. |
