| 摘要 |
PURPOSE:To obtain an RAM of low power consumption, by driving a memory cell only when the writing or reading is carried out via a clock signal supplying means containing a prescribed gate circuit, etc. CONSTITUTION:An AND gate 1 of a signal supplying means CLS is opened by the writing or reading instruction signal through an OR gate 2. Thus a clock pulse phi is supplied to a clock signal line CL. Thus a memory cell D11 is driven via a bit line charge-up means BC only in the writing or reading mode and not driven in the stand-by mode. As a result, the power consumption is reduced for a static RAM. |
