发明名称 Digital-electronic timing mechanism
摘要 In this digital-electronic timing mechanism with a data and command input device, with a display device for the time, the date and/or the event data, with a time-controlled clock generator, with a function-specific computing unit or with a programmable microcomputer, with an external read/write memory, with a read/write encoding system which can be operated via the command input device and with a plurality of switching outputs, the data which are to be entered via the data and command input device (3), for example for the time and for the events are, according to the invention, initially written into a buffer (11) in a format which can be represented on a display device in the sequence time, events before being stored in memory cells of the read/write memory (2) for the purpose of error detection from the respective input. In the buffer (11), the data run through an error detection (8) during the input, the limit values of which are prescribed by an error encoding system (9). When positive evaluation by the error encoding system (9) takes place, the data are overwritten directly and automatically from the buffer (11) into the read/write memory (2). <IMAGE>
申请公布号 DE3123711(A1) 申请公布日期 1983.01.05
申请号 DE19813123711 申请日期 1981.06.15
申请人 DIETER GRAESSLIN FEINWERKTECHNIK 发明人 KAMMERER,GERD;HILS,SIGBERT
分类号 G04G15/00;(IPC1-7):G04G15/00;G04C23/08 主分类号 G04G15/00
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