| 摘要 |
PURPOSE:To receive next cycle data only when an error occurs, by controlling the reception of data through a holding circuit which respectively holds an error signal reception state and the state of a control signal to a register to which data is transferred. CONSTITUTION:If data transferred from a storage device 1 to a register 10 has an error, the error detecting and correcting circuit 3 of the device 1 generates an error detection signal, and an FF4 whose operation timing is controlled by a clock holds the state wherein the error signal is received and closes an AND gate 6. Consequently, the setting signal B of the register 10 is intercepted and at the same time, an FF5 holds the state of a signal B. Hold outputs of FF 5 and 6 are applied through an AND gate 7, an OR gate 8, and an AND gate 9 opened by a next clock to the register 10, which receives transferred data after the error is corrected by the circuit 3. Therefore, transfer information is received in a next cycle only when an error occurs, so that the data transfer system proves a high processing speed. |
