发明名称 INTEGRATION TYPE A/D CONVERTER
摘要 PURPOSE:To decrease the processing time for A/D conversion, by obtaining a compensation value with one calibration cycle, through the compensation period obtained by a charge balancing operation at the calibration cycle. CONSTITUTION:A switch S4 is turned on and an integration output Vo is made equal to an instantaneous voltage Vc of a comparators 2. When a calibration starting signal is applied to a control circuit 12, a switch S2 is turned on, the Vc is applied to an integrator 10 and the integration output Vo is increased. When the integrated output Vo is greater than the Vc, the switch S1 is turned on, a reference voltage VR1 is applied to the integrator 10 and the integrated output V0 is decreased. When the Vo is smaller than the Vc, the switch S2 again turns on and the Vo is increased. The switch operation is repeated, the V0 moves around the Vc and keeps equilibrium. Thus, the compensation period can be obtained from the period of turning on of the switch S2.
申请公布号 JPS57212824(A) 申请公布日期 1982.12.27
申请号 JP19810097994 申请日期 1981.06.24
申请人 TOUKOU KK 发明人 YONEYAMA JIYUICHI
分类号 H03M1/52;H03M1/10;(IPC1-7):03K13/20 主分类号 H03M1/52
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