发明名称 DEMODULATED DATA CHECK SYSTEM
摘要 <p>PURPOSE:To read surely normal demodulated data, by comparing demodulated data, which is inputted plural times, with every data different in value successively and outputting coincident data when the repeat number reaches a certain value. CONSTITUTION:The first demodulated data is stored in the first buffer 3, and the first gate circuit 2 is turned off. Second and third gates 2' and 2'' are turned off first. The second demodulated data is compared with the first demodulated data in the first comparing circuit 4. If they coincide with each other, output ''1'' is sent to the first coincidence number counting circuit 5. The thrid and following demodulated data are operated similarly. If, for example, the third demodulated data is not coincident, ''0'' is outputted and is inverted to ''1'' by an inverter 8-0, and a controlling circuit 6 turns on the second gate 2'. Thus, the third demodulated data is stored in the second buffer 3'. Under this state, if the fourth demodulated data is coincident, 1 is added to the count value. The similar operation is repeated hereafter; and when any counted value reaches a certain value, data of a corresponding buffer 3 is outputted through an OR circuit 9.</p>
申请公布号 JPS57212576(A) 申请公布日期 1982.12.27
申请号 JP19810098585 申请日期 1981.06.25
申请人 FUJITSU KK 发明人 HOSHINO EIICHI;SHINODA ICHIROU
分类号 G06K7/00;(IPC1-7):06K7/00 主分类号 G06K7/00
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