发明名称 BIT SYNCHRONIZATION ADJUSTER
摘要 <p>A data processing system of the kind in which there is a transmission of a code format having a pattern that provides a plurality of reversals 1011010 etc. from which it is desirable to maintain bit synchronization for the incoming data once initial synchronization is obtained. The system being characterized in this that after a first synchronization codeword is recognized at least a part of any following synchronization codeword is sampled at least twice (or three times) per bit and compared with the known structure of the bits of a known synchronization codeword to enable the bit structure of best fit with the known bit structure to be accepted by the system to sample the incoming data. The best fit may conveniently be a running total or summation of least errors when compared with the structure.</p>
申请公布号 WO1982004515(A1) 申请公布日期 1982.12.23
申请号 GB1982000161 申请日期 1982.05.28
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址