| 摘要 |
<p>Circuitry for generating a virtually jitter free delay relative to a start pulse and for generating such delays over both integer and non-integer multiples of the time interval between timing pulses. The circuitry includes delay circuitry and signal generating circuitry. The delay circuitry is responsive to the start pulse and to the timing pulses for generating first and second signal edges. The second signal edge occurs later in time than the first signal edge, and both signal edges occur following the start pulse and in timed relation to the timing pulses. The signal generating circuitry is connected to the delay circuitry and has an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuitry is responsive to the start pulse for initiating the timing cycle, the first signal edge for interrupting the timing cycle, and the second signal edge for reinitiating the timing cycle. The output signal begins in timed relation to the start pulse and terminates in timed relation to the end of the timing cycle following interruption.</p> |
