发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To shorten the time for a test of the titled device provided with a multiple stage frequency dividing circuit by a method wherein the device is provided with a gate circuit transmitting reference frequency signals into a intermediate frequency dividing stage. CONSTITUTION:A reference frequency signal OSC are divided frequency-wise and amultiple stage frequency dividing circuit is formed of T type flip-flops F1-Fn supplying frequency divided signals into a controlling circuit CONT exemplifiedly belonging in a camera. Provided between the flip-flops Fm and Fm+1 is a gate network consisting of AND gates G1 and G2 and OR gate G3 which selectively transmits Fm output signals and reference frequency signals OSC into the flip-flop Fm+1 in the next stage in compliance with controlling signals C. In a test, when ''1'' is used as a controlling signal C, a higher frequency goes into the dividing stage Fm+1-Fn, enabling a divided frequency signal formed in a very short period of time.
申请公布号 JPS57206058(A) 申请公布日期 1982.12.17
申请号 JP19810089523 申请日期 1981.06.12
申请人 HITACHI SEISAKUSHO KK 发明人 SHIMOKAWA RIYUUSHI
分类号 G03B7/091;G01R31/316;H01L21/70 主分类号 G03B7/091
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