| 摘要 |
PURPOSE:To obtain a circuit controlling system which does not require two kinds of loop transmission lines like as the Oregon system, by installing an FIFO buffer memory having a size which exceeds the largest frame of transmitting information to each station. CONSTITUTION:When an address added to transmitting data coincides with the address of said station, a coincidence signal 29 is outputted from an address coincidence detector 5 and input of succeeding data into a repeating delaying factor 4 is prevented, and, at the same time, a gate 9 is closed by a controlling circuit 7. Therefore, the data way at the downstream of said station is set to ''vacant'' condition. Moreover, the controlling circuit closes a gate 11 and opens a gate 13, and successively takes out data stored in an FIFO buffer memory 6 through the gate 13. When the controlling circuit 7 takes out the final information of one data frame, it discriminates that the FIFO buffer memory 6 is vacant and closes the gate 13, and thus, terminates the receiving operation. |
