发明名称 INTERRUPTION PROCESSING SYSTEM
摘要 PURPOSE:To simplify a circuit element by generating and applying pulses as a direct interruption request signal to an interrupting circuit at intervals which are greater than the algebraic sum of a prescribed period and interruption service time. CONSTITUTION:A timer 9 generates negative pulses at prescribed intervals and those pulses are supplied as an interruption request signal IR to an interrupting circuit 1. Once detecting an edge of the signal IR, the circuit 1 supplies an interruption signal INT to a CPU2. The CPU2 receives the signal INT and supplies an interruption response signal INTA to the circuit 1. The pulse intervals of the signal IR are greater than the sum of the time between the supply of the signal INT from the circuit 1 to the CPU to the supply of the signal INTA from the CPU to the circuit 1, and the interruption service time of the CPU2. When the signal INTA is supplied, the level of the signal IR is held, so the circuit 1 assigns priority to the timer 9. After sending the signal INTA, the CPU2 performs the service of interruption to the timer 9.
申请公布号 JPS57203145(A) 申请公布日期 1982.12.13
申请号 JP19810088240 申请日期 1981.06.10
申请人 TOKYO SHIBAURA DENKI KK 发明人 UEDA YASUSHI
分类号 G06F9/48 主分类号 G06F9/48
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