| 摘要 |
PURPOSE:To obtain a high-speed bipolar data latching circuit less in gates for the latch circuit, with high speed and low power, by forming the circuit through the combination of three NOR gates. CONSTITUTION:A latch circuit consists of 3 NOR gates A,B and C, and data D and a clock C are inputted to the NOR gate A. An inverted clock C' and an output of the NOR gate C are inputted to the NOR gate B. Connection is made for the NOR gate C so that the output of the gates A and B is inputted. Thus, the data latch is made with the logical operation as shown in an equation. Through the formation of the circuit, a higj-speed bipolar data latching circuit with less gate numbers and low power can be obtained. |
