| 摘要 |
PURPOSE:To reduce the capacitance of the side wall as well as to prevent the lowering of maximum oscillation frequency of the title transistor by a method wherein the part on the substrate which comes in contact with a junction side wall is formed into a layer with specific resistance, semiconductivity and insulating property higher than those of the substrate. CONSTITUTION:A high specific resistance buffer layer 2, and N type active region 3, and an Fe-added semiinsulating GaAs layer 4 are grown by an epitaxial method on a chrome-added semiinsulating GaAs layer 1. An insulating film 5 is formed on the semiinsulating GaAs layer 4, the insulating material located in the region which will be used for the source and drain of the field-effect transistor is removed, and silicon is implanted using ion-implanting method. A heat treatment is performed in order to activate the implanted ion and to recover the damage received while the ion implantation is performed, and a source region 6 and a drain region 7 are formed. Then, an aperture section is provided by removing the insulating material whereon a gate section will be formed, a Pt is formed at this aperture section, and then a heat treatment is performed. Accordingly, a Pt/As compound is chiefly formed, and the junction of a gate region 8 is also formed in the active region 3. |
