发明名称 VERBUNDARCHITEKTUR FÜR EIN HOCHGRADIG PARALLELES SKALAR/VEKTOR-MULTIPROZESSORSYSTEM
摘要 A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.
申请公布号 DE69033272(D1) 申请公布日期 1999.10.07
申请号 DE1990633272 申请日期 1990.12.27
申请人 CRAY RESEARCH INC., EAGAN 发明人 CHEN, STEVE;SIMMONS, FREDERICK;SPIX, GEORGE;WILSON, JIMMIE;MILLER, EDWARD;ECKERT, ROGER;BEARD, DOUGLAS
分类号 G06F12/06;G06F9/30;G06F9/32;G06F9/38;G06F9/44;G06F9/45;G06F11/36;G06F15/16;G06F15/173;G06F15/78;G06F15/80;G06F17/16;(IPC1-7):G06F13/18 主分类号 G06F12/06
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