VERBUNDARCHITEKTUR FÜR EIN HOCHGRADIG PARALLELES SKALAR/VEKTOR-MULTIPROZESSORSYSTEM
摘要
A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.
申请公布号
DE69033272(D1)
申请公布日期
1999.10.07
申请号
DE1990633272
申请日期
1990.12.27
申请人
CRAY RESEARCH INC., EAGAN
发明人
CHEN, STEVE;SIMMONS, FREDERICK;SPIX, GEORGE;WILSON, JIMMIE;MILLER, EDWARD;ECKERT, ROGER;BEARD, DOUGLAS